The present invention relates to electronic circuits, and more particularly, to clock compensation circuits.
A phase locked-loop (PLL) is a circuit that regenerates and reconditions an input clock signal for use inside an integrated circuit. A PLL can also be used to re-broadcast clock signals over a long trace. In addition, a PLL can multiply an input clock signal by a scaled factor that reduces the need to send a high speed clock in the system. A PLL can also eliminate skew in a clock signal.
In many integrated circuit (IC) chips, an output clock signal of a PLL is transmitted through a clock routing network before reaching a destination circuit on the IC chip. A long clock routing network can introduce significant phase and timing delays into an output clock signal of a PLL. Many applications would benefit from techniques that reduce phase and timing delays in clock signals on an IC.